1. Field of the Invention
The invention relates to an impact ionization field-effect transistor (I-MOS or I-MOSFET). More particularly, the invention relates to an I-MOS in which device degradation caused by hot carrier injection into a gate oxide is prevented.
2. Description of Related Art
Field-effect transistors typically include source, drain, and gate contacts and/or terminals. The characteristics of a channel region between the source and drain are controlled by applying a voltage to the gate contact in which the gate is separated from the channel by an insulating layer such as an oxide layer. Source, drain and channel typically include a semiconductor material. Subject to the set-up of the field-effect transistor, a depletion region is formed between the source and drain by applying a low voltage to the gate contact. In this setup, the depletion region lacks sufficient mobile charge carriers to enable carrier flow between source and drain. When the gate voltage exceeds a certain threshold, which is called the threshold voltage, an inversion layer is formed in the channel along the gate oxide. The inversion layer includes mobile charge carriers such that a low resistance conducting path enables carrier flow between source and drain.
Above the threshold voltage, i.e. in the ON state of the field-effect transistor, the current between source and drain is limited by the channel resistance. For voltages below the threshold voltage, the inverse sub-threshold slope S, where the inverse sub-threshold slope S is denoted byS=[d(log10ID/dVG]−1 with ID being the drain current, and VG being the gate voltage, characterizes the required increase of the gate voltage resulting in a slope of the current in decades (in a logarithmic scale). The inverse sub-threshold slope may be used as a measure for switching characteristics of the field-effect transistor. The lower the inverse sub-threshold slope value is, the faster switching can be achieved between OFF and ON states and vice versa. One of the main obstacles for improving the performance of conventional field-effect transistors is the fundamental room-temperature (RT) limit of the inverse sub-threshold slope of about 60 mV/decade set by the Fermi distribution function.
A device having inverse sub-threshold slope values lower than about 60 mV/decade is the impact ionization field-effect transistor. The impact ionization field-effect transistor is basically represented by a p-i-n diode with a partially gated intrinsic region. This device is built on the effect of impact ionization in the channel triggered by a modulation of the gate voltage followed by an avalanche multiplication of ionization as an internal multiplication mechanism. For generating the avalanche in ionization, the device is tuned into breakdown by modulating the gate voltage. For enabling such tuning into breakdown, the device is biased close to the breakdown voltage. Impact ionization field-effect transistors may exhibit very steep transitions from OFF state to ON state with an inverse sub-threshold slope of about 10 mV/dec at 300 K.
FIG. 1 illustrates a schematic cross-section of an impact ionization field-effect transistor (I-MOS) according to the state of the art. The I-MOS 01 is basically formed by a p-i-n diode with a p-doped region 02, an n-doped region 03 and an intrinsic region 04, i.e. the channel between the p-doped region 02 and the n-doped region 03. The intrinsic region 04 is partially gated by a gate 05 arranged above a part of the intrinsic region 04. A gate dielectric insulator 06, typically a gate oxide, is arranged between the gate 05 and the intrinsic region 04. The p-i-n structure is built on a buried oxide 07.
The I-MOS 01 is reverse biased close to breakdown. The I-MOS 01 is tuned in and out of breakdown by modulating the gate voltage. When tuned into breakdown impact ionization occurs followed by avalanche multiplication in order to create an internal carrier multiplication mechanism.
Such impact-ionization transistors based on field-effect control are known, for example, from US 2006/0113612 A1, US 2006/0125041 A1 or US 2006/0220086 A1.
FIG. 2 shows a three-dimensional perspective view of the I-MOS 01 according to FIG. 1. The drawing includes an energy potential diagram 08 plotted above the device 01. It can be observed from the energy potential diagram 08 that charge carriers become accelerated towards the gate oxide 06, as indicated by the arrow. This effect is called hot carrier injection into the gate oxide which leads to a hot carrier degradation of the gate oxide after a few voltage sweeps, in turn leading to a degradation of the device characteristics. The presence of significant hot carrier effects, in particular the injection of charge carriers into the gate dielectric leads to a shift of the threshold voltage and a degradation of the inverse sub-threshold slope over time. In high performance logic applications such effects are not desired.